A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression
In: IEEE Journal of Solid-State Circuits, Jg. 57 (2022-06-01), S. 1824-1840
Online
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Zugriff:
This article presents a multipolar neural stimulation and mixed-signal neural data acquisition (DAQ) chipset for fully implantable bi-directional brain-computer interfaces (BD-BCIs). The stimulation system employs four 40 V compliant current-stimulators, each capable of sourcing/sinking a maximum 12.75 mA stimulation current, connected to 16 output channels through a high-voltage (HV) switch fabric. A novel time-based charge balancing (TBCB) technique is introduced to reduce the residual voltage on the electrode-electrolyte interface during the inter-pulse time interval, achieving 2 mV charge balancing precision. Additionally, an analytical study of the charge balancing accuracy for the proposed technique is provided. The recording system incorporates a dual-mode DAQ architecture that consists of a 32-element front-end array and a mixed-signal back-end including analog-to-digital converters (ADCs) for both training (i.e., full-band) and decoding (i.e., baseband) operations. Leveraging the flexibility of the multipolar operation, stimulation-side contour shaping (SSCS) artifact cancellation is adopted to significantly suppress stimulation artifacts by up to 45 dB. SSCS method prevents the recording front-ends from saturation and greatly relaxes the dynamic range requirement of the recording system, enabling a truly bi-directional operation. The prototype chipset is fabricated in an HV 180-nm CMOS process and demonstrates a significant performance improvement compared to the prior art.
Titel: |
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression
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Autor/in / Beteiligte Person: | Pu, Haoran ; Do, An H. ; Nenadic, Zoran ; Malekzadeh-Arasteh, Omid ; Ahmad Reza Danesh ; Heydari, Payam |
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Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 57 (2022-06-01), S. 1824-1840 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2022 |
Medientyp: | unknown |
ISSN: | 1558-173X (print) ; 0018-9200 (print) |
DOI: | 10.1109/jssc.2021.3108578 |
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