Ultra low voltage static carry generate circuit
In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010-05-01
Online
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Zugriff:
In this paper we present an ultra low-voltage static CMOS carry generate circuit. The circuit may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuit show an improved performance compared to standard CMOS in terms of delay. Preliminary results indicate a reduced delay to approximately 1/10 of a standard CMOS design. A 32 bit serial carry chain is simulated and the delay is compared to a traditional CMOS carry chain. Simulated data for a ST 90nm CMOS process are included.
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Ultra low voltage static carry generate circuit
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Autor/in / Beteiligte Person: | Berg, Yngvar |
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Zeitschrift: | Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010-05-01 |
Veröffentlichung: | IEEE, 2010 |
Medientyp: | unknown |
DOI: | 10.1109/iscas.2010.5537346 |
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