A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry
In: Journal of Circuits, Systems and Computers, Jg. 29 (2019-08-13), S. 2050095-2050095
Online
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Zugriff:
A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.
Titel: |
A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry
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Autor/in / Beteiligte Person: | Wang, Deng-Shian ; Hsieh, Chia-Lung ; Hou, Zong-You ; Wang, Chua-Chin |
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Zeitschrift: | Journal of Circuits, Systems and Computers, Jg. 29 (2019-08-13), S. 2050095-2050095 |
Veröffentlichung: | World Scientific Pub Co Pte Lt, 2019 |
Medientyp: | unknown |
ISSN: | 1793-6454 (print) ; 0218-1266 (print) |
DOI: | 10.1142/s0218126620500954 |
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