CMOS Design and Analysis of Four-Quadrant Analog Multiplier Circuit for LF Applications
In: Lecture Notes in Electrical Engineering ISBN: 9789811508288; (2019-12-17)
Online
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Zugriff:
Low-frequency analog integrated circuit design is a challenging task considering the threat imposed by flicker noise. This paper presents design and analysis of analog multiplier circuit using p-channel MOS transistor, in contrast to the traditional approach of designing using n-channel MOS transistor. Exhaustive simulation using SCL 180 nm process technology is performed. This includes dc, transient, and harmonics analysis. We derive compact analytical model of various performance parameters and compare it with simulation results. Good matching between the two has been obtained. The application of multiplier circuit for demodulation purpose is shown.
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CMOS Design and Analysis of Four-Quadrant Analog Multiplier Circuit for LF Applications
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Autor/in / Beteiligte Person: | Pandit, Soumya ; Abhishek Kumar Gond |
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Quelle: | Lecture Notes in Electrical Engineering ISBN: 9789811508288; (2019-12-17) |
Veröffentlichung: | Springer Singapore, 2019 |
Medientyp: | unknown |
DOI: | 10.1007/978-981-15-0829-5_28 |
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