Sensing Characteristic Enhancement of CMOS-Based ISFETs With Three-Dimensional Extended- Gate Architecture
In: IEEE Sensors Journal, Jg. 21 (2021-04-01), S. 8831-8838
Online
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Zugriff:
As the CMOS-based ion-sensitive field-effect transistor (ISFET) is scaling down to achieve a compact sensing array with high spatial resolution, reduction of sensing layer capacitance attenuates capacitive coupling efficiency of environmental input signals and decreases sensitivity performance. To address this issue, a concept of three-dimensional (3D) sensing structure is proposed and examined in this study. This can increase the sensing layer capacitance for a given footprint area. Based on our designs, a series of 3D sensing structures can be implemented with a standard CMOS foundry service and CMOS-compatible post processes. Our experimental results show that an $8.5^{2}\mu \text{m}^{2}$ footprint design of the 3D sensing structure can obtain approximately 2-fold increase in transconductance compared with a traditional ISFET with the same footprint. This enables pH sensitivity to be improved 1.5-fold in current response and 1.15-fold in voltage response. Therefore, the proposed 3D-structure ISFET can pave the way toward an ISFET sensing array with high sensitivity and high spatial resolution.
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Sensing Characteristic Enhancement of CMOS-Based ISFETs With Three-Dimensional Extended- Gate Architecture
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Autor/in / Beteiligte Person: | Wang, Rui-Xing ; Lin, Chih-Ting ; Teng, Nan-Yuan ; Wu, Yi-Ting |
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Zeitschrift: | IEEE Sensors Journal, Jg. 21 (2021-04-01), S. 8831-8838 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 2379-9153 (print) ; 1530-437X (print) |
DOI: | 10.1109/jsen.2021.3052772 |
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