Design and simulation of a DAC-calibrated 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS
In: Analog Integrated Circuits and Signal Processing, Jg. 87 (2016-04-06), S. 327-340
Online
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Zugriff:
This paper presents transistor-level design of a continuous-time delta-sigma modulator with 150 MHz bandwidth in 28 nm CMOS process with 1.4/0.85 V supply. Architectural-level design tradeoff for the high-speed and high-resolution requirement is analyzed. A stand-alone DAC calibration scheme is proposed for the linearization of the high-speed modulator. Simulation results show that the modulator achieves signal-to-noise-and-distortion ratio of 71 dB and spurious free dynamic range of 90 dB. The chip occupies 1.9 mm2 and consumes 213 mW.
Titel: |
Design and simulation of a DAC-calibrated 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS
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Autor/in / Beteiligte Person: | You, Y. ; Wu, Guoying ; Gui, Ping ; Sun, Kexu ; Azadet, Kamran ; Wang, Rui ; Chen, Jinghong |
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Zeitschrift: | Analog Integrated Circuits and Signal Processing, Jg. 87 (2016-04-06), S. 327-340 |
Veröffentlichung: | Springer Science and Business Media LLC, 2016 |
Medientyp: | unknown |
ISSN: | 1573-1979 (print) ; 0925-1030 (print) |
DOI: | 10.1007/s10470-016-0738-9 |
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