Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
In: Semiconductor Science and Technology, Jg. 23 (2007-12-06), S. 015004-15004
Online
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Zugriff:
In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.
| Titel: |
Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
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| Autor/in / Beteiligte Person: | Hwi Huang Chen ; Chih Hung Lin ; Chen, Chien-Hung ; Tzu Ping Chen ; Ko, Joe ; Tsung Yu Yang ; Tsung Min Hsieh ; Jhyy Cheng Liou ; Jian Hao Chen ; Wen Luh Yang ; Lee, Chien-Hsing ; Lai, Chao-Sung ; Wu Chin Peng ; Woei Cherng Wu ; Chao, Tien-Sheng ; Ming Wen Ma |
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| Zeitschrift: | Semiconductor Science and Technology, Jg. 23 (2007-12-06), S. 015004-15004 |
| Veröffentlichung: | IOP Publishing, 2007 |
| Medientyp: | unknown |
| ISSN: | 1361-6641 (print) ; 0268-1242 (print) |
| DOI: | 10.1088/0268-1242/23/1/015004 |
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