A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology
In: IEICE Electronics Express, Jg. 8 (2011), S. 1245-1251
Online
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Zugriff:
A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65nm CMOS process, and the power consumption is 1.52mW at 250MHz and 5.83mW at 1GHz, respectively.
| Titel: |
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology
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| Autor/in / Beteiligte Person: | Shen, Sung-En ; Chung, Ching-Che ; Sheng, Duo |
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| Zeitschrift: | IEICE Electronics Express, Jg. 8 (2011), S. 1245-1251 |
| Veröffentlichung: | Institute of Electronics, Information and Communications Engineers (IEICE), 2011 |
| Medientyp: | unknown |
| ISSN: | 1349-2543 (print) |
| DOI: | 10.1587/elex.8.1245 |
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