A Quadrature Frequency Synthesizer with 118.7-fs Jitter, <−64 dBc Spurs and >27.94% Locking Range for Multiband 5G mmW Applications
In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020-10-01
Online
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Zugriff:
This paper presents a quadrature frequency synthesizer (QFS) utilizing a switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving a wide frequency tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in a 55 nm CMOS process, achieving a reference spurs of −64 to −72 dBc, an in-band phase noise of −81.7 to −87 dBc/Hz at 100 kHz offset and an out-of-band phase noise of −119.1 to −125.4 dBc/Hz at 10 MHz offset, respectively, over the entire 19.89 to 26.35 GHz frequency locking range. The RMS jitter for a 19.89 GHz carrier is 118.7 fs, corresponding to a jitter FOM of −238.47 dB. The chip occupies a die area of 1.31 × 2.13 mm2 including the testing pads and dissipates 101 mW of power.
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A Quadrature Frequency Synthesizer with 118.7-fs Jitter, <−64 dBc Spurs and >27.94% Locking Range for Multiband 5G mmW Applications
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Autor/in / Beteiligte Person: | Shi, Chunqi ; Chen, Jinghong ; Zhang, Zitong ; Zhang, Runxi ; Fan, Qingjun ; Yang, Hui |
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Zeitschrift: | 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020-10-01 |
Veröffentlichung: | IEEE, 2020 |
Medientyp: | unknown |
DOI: | 10.1109/iscas45731.2020.9181060 |
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