Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology
In: Journal of Instrumentation, Jg. 11 (2016-12-01), S. C12001
Online
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Zugriff:
The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e− for a detector capacitance CDET = 160 fF.
Titel: |
Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology
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Autor/in / Beteiligte Person: | Kleczek, Rafal |
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Zeitschrift: | Journal of Instrumentation, Jg. 11 (2016-12-01), S. C12001 |
Veröffentlichung: | IOP Publishing, 2016 |
Medientyp: | unknown |
ISSN: | 1748-0221 (print) |
DOI: | 10.1088/1748-0221/11/12/c12001 |
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