Time of arrival measurement for indoor distance monitoring in 130-nm CMOS

A new architecture for Vernier-based frequency-to-voltage/digital converter (VFVDC) is proposed for time difference of arrival (TDOA) measurement using a frequency domain approach. The VFVDC is employed for indoor distance monitoring using an RFID front end. The proposed architecture employs an injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need the complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital converters. The oscillator consumes 14.4 μ W and 1.15 mW from 0.4 V and 1.2 V supplies. The total power consumption of the entire chip is only 0.65 mW and 7.6 mW from 0.4 V and 1.2 V supplies while operating at 1.615 MHz and 22.55 MHz, respectively. The design was implemented in 130-nm CMOS process and has a core area of 0.1 mm 2 , one of the lowest in reported literature. The proposed VFVDC is reconfigurable and achieves a large detectable range of 1–300 mm, with a fine distance resolution of 3 mm/kHz in a small die size while consuming low power with FoM of 5.78 fA-s/m.