[Untitled]
Southern Federal University, 2018
Online
unknown
Zugriff:
For transition to advanced nanotechnologies designing it is needed to consider the influence of various factors, including the degradation of the electrical parameters of transistors and the increased leakage. In general, the known methods and algorithms for analyzing the above factors are based on models that are applied only at the schematic level. Because of the complication of element models and the increase in the degree of integration, the dimension of the complete simulation problem, taking into account the entire set of parameters, has increased dramatically. This fact indicates a decrease in the efficiency of circuit simulation for such cases in terms of time and machine costs. The solution to this problem can be the transition from schematic level to a higher level of abstraction. Unlike the existingmethods of reducing circuits that are aimed at reducing the size of RC-circuits, the generalized Gaussian method can be applied to the description of a block at the transistor level. It allows representing an arbitrary structure of an element or a CMOS IC block in the form of a set of two bipoles representing conductive paths connecting output of circuit with a power/ground bus. At each step of the generalized Gaussian method selected node is removed from the transistor circuit, and instead of the nets connected to this node, new ones appear – serial or parallel combinations of existing nets. A time-logical model of the IC element (block) is proposed. It is formed by the Gauss elimination method and combines the logic function and block structure at the transistor level, which allows moving from schematic level to timelogic level of analysis. It also allows calculating the time characteristics of the circuit as a function of an arbitrary set of transistor parameters (channel length, threshold voltage, etc.) and speed up the characterization process through preliminary analysis at the time-logic level with the Spice simulation for a limited subset of test sequences.
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Autor/in / Beteiligte Person: | Ryzhova , D. I. ; Schelokov , A. N. ; Gavrilov, S.V. |
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Veröffentlichung: | Southern Federal University, 2018 |
Medientyp: | unknown |
DOI: | 10.23683/2311-3103-2018-4-6-14 |
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