A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage
In: IEEE Journal of Solid-State Circuits, Jg. 52 (2017-03-01), S. 657-668
Online
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Zugriff:
A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a third-order filter implemented with a lossless integrator and a multiple-feedback single-amplifier biquadratic filter with embedded loop stability compensation. An active summing block is implemented by employing a common-gate current buffer followed by a transimpedance amplifier. This combination relaxes the specification requirements of the operational amplifier by making its required BW independent of the closed-loop gain. The proposed technique achieves optimum BW with reduced power consumption, making it functional for over gigahertz operation. Fabricated in a standard 40-nm CMOS technology, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise-and-distortion ratio of 65.5 dB over 75-MHz BW while consuming 22.8 mW of power. The obtained Walden's figure of merits is 98 fJ/conv-step.
Titel: |
A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage
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Autor/in / Beteiligte Person: | Edward, Alexander ; Palermo, Samuel ; Shafik, Ayman ; Silva-Martinez, Jose ; Briseno-Vidrios, Carlos |
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Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 52 (2017-03-01), S. 657-668 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2017 |
Medientyp: | unknown |
ISSN: | 1558-173X (print) ; 0018-9200 (print) |
DOI: | 10.1109/jssc.2016.2634700 |
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