TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS

A physical assessment of the lateral gate-all-around (GAA) nanosheet transistor (NSFET) at the G40M16 node (gate length = 12 nm projected for 2028) of the newly defined beyond-Moore International Roadmap for Devices and Systems [~5 nm node of the predecessor International Technology Roadmap for Semiconductors (ITRS)], supported by 3-D numerical device simulations and based on a proposed per-footprint scheme, is presented. The traditional evaluation scheme to gauge the performance of the transistor ``per effective channel width'' is shown to be improper due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, obfuscates the dependence of current on sheet/channel width and undermines the presumed added benefit of short-channel effect (SCE) control in the GAA device. The NSFET provides a flexible sheet width, as opposed to that of the FinFET with discrete fins, but the allowed range of sheet width is limited due to significant parasitic capacitance at a relatively narrow width and degraded SCE control and increased resistance for desired wide width. Furthermore, the nanosheet (NS) device density is undermined at a narrow width, especially for decreasing pitch. The FinFET is shown to be a favorable alternative to the NSFET even at the G40M16 node.