A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
In: IEEE Journal of Solid-State Circuits, Jg. 52 (2017-07-01), S. 1885-1903
Online
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Zugriff:
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order $\Delta \Sigma $ -TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73–3.38 GHz (after a $\div $ 2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than −110-dBc/Hz in-band PN and occupies an active area of 0.5 mm2. With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fs $_{{\mathrm{rms}}}$ jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.
Titel: |
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
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Autor/in / Beteiligte Person: | Lu, Ping ; Shahmohammadi, Mina ; Wu, Ying ; Robert Bogdan Staszewski ; Chen, Yue |
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Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 52 (2017-07-01), S. 1885-1903 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2017 |
Medientyp: | unknown |
ISSN: | 1558-173X (print) ; 0018-9200 (print) |
DOI: | 10.1109/jssc.2017.2682841 |
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