Dual-Threshold CMOS Technique for Pass-Transistor Adiabatic Logic with PMOS Pull-Up Configuration
In: Lecture Notes in Electrical Engineering ISBN: 9783642197055; (2011)
Online
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Zugriff:
DTCMOS (Dual-threshold CMOS) has been proven as an effective way to reduce sub-threshold leakage consumption. P-type logic circuits that consist mostly of PMOS transistors can significantly reduce the gate leakage dissipations in nanometer CMOS processes with gate oxide structure. This paper proposes a dual-threshold CMOS scheme for PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the DTCMOS PAL-2P circuits. All circuits are verified with HSPICE using the 65nm CMOS process with gate oxide materials. The PAL-2P circuits using DTCMOS (dual-threshold CMOS) technique exhibit large energy savings, since both sub-threshold and gate leakage dissipations are reduced effetely.
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Dual-Threshold CMOS Technique for Pass-Transistor Adiabatic Logic with PMOS Pull-Up Configuration
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Autor/in / Beteiligte Person: | Ni, Haiyan ; Ye, Lifang ; Hu, Jianping |
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Quelle: | Lecture Notes in Electrical Engineering ISBN: 9783642197055; (2011) |
Veröffentlichung: | Springer Berlin Heidelberg, 2011 |
Medientyp: | unknown |
ISBN: | 978-3-642-19705-5 (print) |
DOI: | 10.1007/978-3-642-19706-2_5 |
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