Improving the Photon Detection Probability of SPAD implemented in FD-SOI CMOS Technology with light-trapping concept

This article proposes a 3D electro-optical simulation method to estimate the Photon Detection Probability (PDP) of Single-Photon Avalanche Diodes (SPAD) implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. In order to improve the PDP of SPAD implemented in FD-SOI CMOS technology, a light-trapping approach is studied, thanks to the patterning of Shallow Trench Insolation (STI) layer and the patterning of Silicon substrate, respectively in the case of Front Side Illumination (FSI) and Back Side Illumination (BSI). An average gain of 50% for wavelengths between 400nm-1000nm and of 200% for wavelengths between 800-1000nm respectively in the case of FSI and BSI are achieved. Based on this study, IC fabrication including several designs of SPAD implemented in FD-SOI CMOS technology with different pattern sizes is launched for future electro-optical characterization.