Electrically active stacking faults in CMOS integrated circuits

The origin and nature of anomalous leakage currents in CMOS (complementary metal‐oxide‐semiconductor) integrated circuits are investigated. Studies of the voltage dependence of the leakage on both devices and p/n junctions show that device leakage originates from individual junctions, and is very similar to that found from electrically active stacking faults (EASF’s) studied by other workers.1 In particular, a power‐law dependence (IR∝VnR) is observed with exponents ranging from n=3–7.5. The onset of the anomalous leakage occurs at reverse‐bias voltages ranging from 2–8 V. Etching studies of junctions with and without the anomalous leakage indicate a high correlation between the presence of the leakage and the occurrence of stacking faults intersecting the p/n junction boundary at the silicon surface. This correlation is confirmed by scanning electron microscope studies in the electron‐beam‐induced‐current (EBIC) mode. Every junction showing the anomalous leakage exhibits one or more EBIC sites along the ...