Noise Margin, Delay, and Power Model for Pseudo-CMOS TFT Logic Circuits

Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits. Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits. In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits. Furthermore, we simplify thosemodels formanual analysis and design optimization. Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs. The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively. In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness.