A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 $\mu \text {m} \times 234\,\,\mu \text{m}$ . The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.