Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 38 (2019-07-01), S. 1345-1358
Online
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Zugriff:
Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address the validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the hybrid quick error detection ( H -QED) approach that overcomes validation and debug challenges for hardware accelerators by leveraging HLS techniques in both the presilicon and post-silicon stages. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it is detected) by 2–5 orders of magnitude with one cycle latencies in presilicon scenarios and bug coverage threefold higher compared to traditional validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs an 8% accelerator area overhead with negligible silicon performance impact for post-silicon stage, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.
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Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
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Autor/in / Beteiligte Person: | Campbell, Keith ; Rupnow, Kyle ; He, Leon ; Yang, Liwei ; Mitra, Subhasish ; Chen, Deming ; Gurumani, Swathi ; Lin, David |
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Zeitschrift: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 38 (2019-07-01), S. 1345-1358 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2019 |
Medientyp: | unknown |
ISSN: | 1937-4151 (print) ; 0278-0070 (print) |
DOI: | 10.1109/tcad.2018.2837103 |
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