Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection
In: 2007 IEEE Custom Integrated Circuits Conference, 2007-09-01
Online
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Zugriff:
We propose novel compact fault recovering flip-flops (CFR-FFs) which can recover timing error and soft error caused by process variation, supply voltage fluctuation, attacking high energy particle, and so on. Those FFs are composed of an error detector and a clock controller, which re-raises a clock to latch correct data upon error detecting. We propose two kinds of CFR-FFs. One is that the clock rises every cycle, and the other is that the clock rises only when data has changed. These FFs were fabricated by a 0.25 mum CMOS process. Error rates were measured by applying a noise signal to the supply voltage. While the error rate was over 46 % for a conventional FF, it was 1.4 % and 2.2 % for each CFR-FF with only 1.41 and 1.65 times area overhead, respectively.
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Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection
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Autor/in / Beteiligte Person: | Fujita, S. ; Yasuda, S. |
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Zeitschrift: | 2007 IEEE Custom Integrated Circuits Conference, 2007-09-01 |
Veröffentlichung: | IEEE, 2007 |
Medientyp: | unknown |
DOI: | 10.1109/cicc.2007.4405832 |
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