Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells
In: IEEE Electron Device Letters, Jg. 32 (2011-08-01), S. 1041-1043
Online
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Zugriff:
International audience; The optimization of the programming voltage and the dimensions of antifuse bitcells is a design challenge due to antagonistic parameters. An optimization approach is presented using a time-dependent dielectric breakdown (TDDB) model. Fowler-Nordheim wear-out current and TBD power-law models are identified using electrical characterizations performed on antifuse bitcells fabricated in standard 40-nm CMOS. The TDDB model allows the calculation of the programming voltage according to a targeted TBD and the antifuse bitcell dimensions. As a result, it was shown that the lowest programming voltage is obtained for a small capacitor, whereas the size of the drift transistor has a second-order impact.
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Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells
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Autor/in / Beteiligte Person: | Allard, Bruno ; Deloge, Matthieu ; Rafik, Mustapha ; Candelier, Philippe ; Le-Roux, Elise ; Damiens, Joel ; (AMPERE), Ampère ; École Centrale de Lyon (ECL) ; Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL) ; Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon) ; Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE) ; STMicroelectronics [Crolles] (ST-CROLLES) |
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Zeitschrift: | IEEE Electron Device Letters, Jg. 32 (2011-08-01), S. 1041-1043 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2011 |
Medientyp: | unknown |
ISSN: | 1558-0563 (print) ; 0741-3106 (print) |
DOI: | 10.1109/led.2011.2158054 |
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