3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

3-D stacks of complimentary metal–oxide–semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13- $\mu \text{m}$ CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and ${10}~\mu \text{m}$ of thickness, linewidth, and space, respectively, along with through Si vias (TSVs) with 10 and $40~\mu \text{m}$ of diameter and depth, respectively. The capacitance of 0.18 nF/mm2 in the effective backside area of 71 mm2 suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by $14\times $ increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the ${t}$ -test value of larger than 4.5.