Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology
In: Microelectronics Journal, Jg. 72 (2018-02-01), S. 86-99
Online
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Zugriff:
It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem.
Titel: |
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology
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Autor/in / Beteiligte Person: | Desai, Madhav P. ; Rao, Nanditha P. |
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Zeitschrift: | Microelectronics Journal, Jg. 72 (2018-02-01), S. 86-99 |
Veröffentlichung: | Elsevier BV, 2018 |
Medientyp: | unknown |
ISSN: | 0026-2692 (print) |
DOI: | 10.1016/j.mejo.2017.12.009 |
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