New Reprogrammable and Non-Volatile Radiation-Tolerant FPGA: RT ProASIC®3

Non-Volatile and Reconfigurable Field Programmable Gate Arrays (FPGAs) present an attractive solution for high-level system integration in various aerospace and military applications. Commercially available Low-Power Flash-based FPGAs, 0.13-μm ProASIC3/L (A3PL) and its extended family product (A3PEL) are non-volatile while providing remote in-system reprogramming to support future design iterations and field upgrades. Flashbased technology provides them the advantage of being a secure, low-power, single-chip solution [Morris, 2006]. Unlike SRAM based-FPGAs, the configuration memories are not volatile and hence don’t require additional non-volatile memory to reload the device configuration data at system-power-up or due to radiation effects [Swift et al., 2004] in addition to Triple Module Redundancy (TMR) of its entire set of configuration bits [Carmichael, 2001]. This reduces cost, power, and initialization time and improves system reliability. However, despite the SEE immunity of their configuration memory, their Floating Gate (FG) switches and CMOS logic gates are susceptible to both effects of the Total Ioninzing Dose (TID) and the Single Event Effects (SEE). For TID effects, the primary issue is the radiation-induced charge loss in the floating gate [Snyder et al., 1989, Cellere et al., 2004, Wang et al., 2004, Guertin et al., 2006], resulting in the change of the FPGA electrical performances (maximum speed, current, etc.). While for SEE, the primary concern resides in the upset of its registers (state of the flip-flop) due to a particle hit, resulting in the disruption of the normal operation of the FPGA-design [Rezgui et al., 2007a & 2007b]. The new Radiation-Tolerant ProASIC3 (RT ProASIC3 or RT3P), sharing the same silicon of the Low-Power A3PL FPGAs is hardened for TID and SEE by software means in a transparent manner to the user [Rezgui et al., 2008a]. The Single Event Transients (SET) tolerance is hardened by single or duplication filtering [Shuler et al., 2005 & 2006, Balasubramanian et al., 2005, Baze et al., 2006, Mavis & Eaton, 2007, Rezgui et al., 2007a] and Single Event Upsets (SEU) are hardened by TMR or Error Detection and Correction (EDAC) to soft error rates less than 10-10 upsets/bit-day and LETth larger than 40 MeV•cm2/mg for clock frequency up to 100 MHz. While their TID limit is improved by simple reprogrammimg of the FPGA resulting in the restoration of the charge loss from their configuration FG swicthes. This chapter describes the employed mitigation techniques for the A3P product family, to attain the radiation levels of the RT-product and presents the results issued from the TID and the SEE characterization of both of the A3P and the A3PL (the Low-Power version of