Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, S. 1-4
Online
unknown
Zugriff:
Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.
5pages, 6 figures
Titel: |
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
|
---|---|
Autor/in / Beteiligte Person: | Krishna, Komala ; Nambath, Nandakumar |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, S. 1-4 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2023 |
Medientyp: | unknown |
ISSN: | 1557-9999 (print) ; 1063-8210 (print) |
DOI: | 10.1109/tvlsi.2023.3276000 |
Schlagwort: |
|
Sonstiges: |
|