Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop
In: Micromachines, Jg. 10 (2019-06-01), Heft 6
Online
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Zugriff:
An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead
and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 ×
and the energy by 1.5 ×
The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2&ndash
18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.
Titel: |
Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop
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Autor/in / Beteiligte Person: | Park, Jaeyoung ; Young Uk Yim |
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Zeitschrift: | Micromachines, Jg. 10 (2019-06-01), Heft 6 |
Veröffentlichung: | MDPI, 2019 |
Medientyp: | unknown |
ISSN: | 2072-666X (print) |
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