Co-Integration of Nano-Scale Vertical- and Horizontal-Channel Metal-Oxide-Semiconductor Field-Effect Transistors for Low Power CMOS Technology
In: Journal of Nanoscience and Nanotechnology, Jg. 12 (2012-07-01), S. 5313-5317
Online
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Zugriff:
In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.
Titel: |
Co-Integration of Nano-Scale Vertical- and Horizontal-Channel Metal-Oxide-Semiconductor Field-Effect Transistors for Low Power CMOS Technology
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Autor/in / Beteiligte Person: | Kim, Garam ; Shin, Hyungcheol ; Park, Byung-Gook ; Kim, Hyun-Woo ; Lee, Jong-Ho ; Kim, Hyungjin ; Kim, Sangwan ; Sun, Min-Chul |
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Zeitschrift: | Journal of Nanoscience and Nanotechnology, Jg. 12 (2012-07-01), S. 5313-5317 |
Veröffentlichung: | American Scientific Publishers, 2012 |
Medientyp: | unknown |
ISSN: | 1533-4880 (print) |
DOI: | 10.1166/jnn.2012.6226 |
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