A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.