A hybrid design approach of PVT tolerant, power efficient ring VCO
In: Ain Shams Engineering Journal, Jg. 11 (2020), Heft 2, S. 265-272
Online
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Zugriff:
This article unveils a new hybrid configuration of ring type VCO (voltage controlled oscillator) consisting of CMOS and current starved inverter to generate full voltage swing. A certain number of such inverters are cascaded alternatively to obtain the output frequency (fosc). The novelty lies in the fact that this design offers a good trade-off of power, frequency and gate count against CMOS based or current starved based design counterpart. In a 90 nm process, the highest fosc achieved for a 7th stage VCO device footprint is 1.78 GHz with a power dissipation of 44.59 µW at a supply and control voltage of 1.2 V and 1 V respectively. The simulated phase noise and output noise of the layout read to be −95.15dBc/Hz and −144.55 dB respectively measured at 1 MHz offset frequency along with the corresponding figure of merit (FOM) of −173.67dBc/Hz. In order to understand the robustness and scalability of the proposed design, the performances are observed using Monte Carlo study and as small as UMC 28 nm CMOS process.
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A hybrid design approach of PVT tolerant, power efficient ring VCO
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Autor/in / Beteiligte Person: | Majumder, Alak ; Maiti, Madhusudan ; Mondal, Abir J. ; Suraj Kumar Saw |
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Zeitschrift: | Ain Shams Engineering Journal, Jg. 11 (2020), Heft 2, S. 265-272 |
Veröffentlichung: | Elsevier, 2020 |
Medientyp: | unknown |
ISSN: | 2090-4479 (print) |
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