Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance
In: 2014 International Conference on Microelectronic Test Structures (ICMTS), 2014-03-01
Online
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Zugriff:
session 10: matching; International audience; The work presented in this paper investigates the possibility of replacing a Lateral Drain Extended MOS (LDEMOS) SOI transistors by a cascode configuration to improve the electrical mismatch performance. The cascode connection of two MOS devices is known to sustain as high drain voltage as LDEMOS SOI transistors and offers the same mismatch robustness of Silicon On Insulator (SOI) MOS transistors. The individual mismatch constants associated to Vt (iA Δvt ), β (iA Δβ/β ) and Id (iA ΔId/Id ) for the presented cascode configuration are shown to have similar values to those reported for individual MOS devices.
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Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance
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| Autor/in / Beteiligte Person: | Rosa, Julien ; Bajolet, A. ; Rahhal, Lama ; Bertrand, Guillaume ; Ghibaudo, Gerard ; STMicroelectronics [Crolles] (ST-CROLLES) ; Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS) |
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| Zeitschrift: | 2014 International Conference on Microelectronic Test Structures (ICMTS), 2014-03-01 |
| Veröffentlichung: | IEEE, 2014 |
| Medientyp: | unknown |
| DOI: | 10.1109/icmts.2014.6841499 |
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