Design and Implementation of a Single Flux Quantum Logic-Based Memory Controller for Josephson-CMOS Hybrid Memory Systems
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020
Online
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Zugriff:
Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2 STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.
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Design and Implementation of a Single Flux Quantum Logic-Based Memory Controller for Josephson-CMOS Hybrid Memory Systems
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Autor/in / Beteiligte Person: | Demirhan, Seda ; Bozbey, Ali ; TOBB ETU, Faculty of Engineering, Department of Electrical & Electronics Engineering ; TOBB ETÜ, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümü |
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Veröffentlichung: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020 |
Medientyp: | unknown |
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