A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC
In: Journal of Instrumentation, Jg. 11 (2016-12-19), S. C12044
Online
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Zugriff:
This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.
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A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC
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| Autor/in / Beteiligte Person: | M. Da Rocha Rolo ; Marconi, S. ; Dellacasa, G. ; Pacher, Luca ; Magazzu, Guido ; Stabile, Alberto ; Gaioni, Luigi ; Ratti, Lodovico ; Re, Valerio ; F. De Canio ; Placidi, Pisana ; Veri, C. ; Demaria, Natale ; Traversi, Gianluca ; Mattiazzo, Serena ; Monteil, Ennio ; Rivetti, Angelo ; Marzocca, Cristoforo ; Paterno, A. ; Licciulli, F. ; Loddo, F. ; Mazza, G. ; Ciciriello, F. |
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| Zeitschrift: | Journal of Instrumentation, Jg. 11 (2016-12-19), S. C12044 |
| Veröffentlichung: | IOP Publishing, 2016 |
| Medientyp: | unknown |
| ISSN: | 1748-0221 (print) |
| DOI: | 10.1088/1748-0221/11/12/c12044 |
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