Performances Evaluation of On-chip Large-Size Tapped Transformer for MEMS applications

This article aims at providing a better behavior understanding and performance evaluation of a large-size passive on-chip tapped transformer when used as a transducer in low-frequency integrated microsystems [30–300 kHz]. Thus, a CMOS-based 1:1 transformer, consisting of 70 turns of 1.6- $\mu \text{m}$ -wide top-level metal spaced by 0.6 $\mu \text{m}$ and with a total length of 1.7 mm, has been investigated and tested. The spatial separation between the two transformer windings was set to 70 $\mu \text{m}$ . An electrical equivalent lumped model has been extracted through an exhaustive specific measurement procedure. The model is useful to simulate and evaluate the voltage transformation ratio (TR) between the two transformer windings. The effects of parasitics and imperfect coupling between transformer windings and through the silicon substrate are outlined from the circuit point of view. We report a magnetic coupling coefficient that does not exceed $k=0.15$ , with a voltage TR of about 0.39 around the resonance frequency of ~5.3 MHz, when the secondary is unloaded. It has been proven that the interwindings capacitance introduced by close conductors of each winding, evaluated to 13 pF, assures the most important role in the power transfer. This article has shown that by optimizing properly the transformer realization and limiting some parasitics elements, the inductive and capacitive links could both play a key role in MEMS transducers through tapped transformers operation around 100-kHz frequencies.