An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 65 (2018-11-01), S. 3756-3768
Online
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Zugriff:
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for
Titel: |
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs
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Autor/in / Beteiligte Person: | Feng Wei Kuo ; Babaie, Masoud ; Cho, Lan-Chou ; Huan-Neng Ron Chen ; Chen, Mark ; Jou, Chewn-Pu ; Robert Bogdan Staszewski |
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Zeitschrift: | IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 65 (2018-11-01), S. 3756-3768 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2018 |
Medientyp: | unknown |
ISSN: | 1558-0806 (print) ; 1549-8328 (print) |
DOI: | 10.1109/tcsi.2018.2855972 |
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