Radiation hard programmable delay line for LHCb calorimeter upgrade
In: Journal of Instrumentation, Jg. 9 (2014-01-13), Heft 01, S. C01016
Online
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Zugriff:
International audience; This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm(2) chip has been implemented in CMOS 0.35 mu m technology.
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Radiation hard programmable delay line for LHCb calorimeter upgrade
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Autor/in / Beteiligte Person: | Machefert, F. ; Gascon, David ; Mauricio, Joan ; Lefrançois, J. ; Duarte, O ; Vilasis, X. ; Picatoste, E. ; Beigbeder, C ; Laboratoire de l'Accélérateur Linéaire (LAL) ; Université Paris-Sud - Paris 11 (UP11)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS) ; LHCb |
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Zeitschrift: | Journal of Instrumentation, Jg. 9 (2014-01-13), Heft 01, S. C01016 |
Veröffentlichung: | IOP Publishing, 2014 |
Medientyp: | unknown |
ISSN: | 1748-0221 (print) |
DOI: | 10.1088/1748-0221/9/01/c01016 |
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