Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models
In: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Jg. 7 (2021), Heft 2, S. 193-200
Online
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Zugriff:
Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- $k$ metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- $V_{\mathrm {DD}}$ scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.
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Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models
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Autor/in / Beteiligte Person: | Chakraborty, Wriddhi ; Cao, Yu ; Raychowdhury, Arijit ; Cao, Ningyuan ; Saligram, Rakshith ; Datta, Suman |
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Zeitschrift: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Jg. 7 (2021), Heft 2, S. 193-200 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 2329-9231 (print) |
DOI: | 10.1109/jxcdc.2021.3131100 |
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