A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm2, including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.
Keywords: 28 GHz; CMOS; phased array antenna; multi-channel; beamforming; transceiver; fifth generation (5G); mm wave; phase and gain control; multimode
The increasing demand for data communication brings about the emergence of 5G communications using mm-wave technology. Mm-wave phased array transceivers support multiple users operating with high data rates using broadband directional links between the mm-wave base stations and mobile devices [[
In this paper, a multimode 28 GHz CMOS fully differential eight-channel BFIC is presented for a phased array transceiver. The BFIC incorporates a differential SPDT switch, which enables multimode operations. It has the capability to operate in 8Tx and 8Rx modes separately as well as in a combined 8Tx8Rx TDD mode. Furthermore, it is capable of operating in the four-channel mode, allowing the independent operation of 4Tx and 4Rx within a single BFIC. This flexibility in operation modes offers a range of choices depending on the specific requirements of the number of antennas. The eight-channel mode can integrate the number of antennas, resulting in a narrow beam, high EIRP, and improvement in the SNR suitable for mm-wave base stations. Furthermore, the ability of the BFIC to support a four-channel mode enhances its suitability for mobile devices by providing a compact and power-efficient chip solution.
The RF-phase-shifting beamforming architecture has been adopted considering the power consumption, chip size, and design complexity. The block diagram of the 28 GHz eight-channel CMOS fully differential multimode BFIC is shown in Figure 1. All the circuits in the chip have a differential structure. A differential design reduces coupling between the channels and improves isolation. A simple and high-performance unit channel structure is used. Each channel consists of a differential two-stage bi-directional amplifier, a six-bit phase shifter, and a three-bit digital step attenuator. The multiple channel Tx/Rx signals are split or combined using a two-way power divider. The fully differential SPDT switch is implemented to control the multimode operations. The bi-directional amplifiers were distributed to deliver enough power to each channel. A Marchand balun is implemented in the common signal path of the four-channel for transforming single-ended and differential signals. To realize the compact phased array antenna system, the bi-directional architecture is employed. The area reduction is realized by sharing the passive phase shifters, attenuators, and power divider between the TX mode and the RX mode.
The 28 GHz eight-channel BFIC has the capability to operate in multimode, including the 8Tx and 8Rx modes separately, the 8Tx8Rx TDD mode, and also the 4Tx and 4Rx mode independently. When the SPDT switches are in the default state (off state) and all the eight-channel are set to Tx mode, it operates in 8Tx mode, as shown in Figure 2a. When all the eight-channel are set to Rx mode, then it operates as the 8Rx mode, as in Figure 2b. Additionally, by controlling the Tx/Rx mode select switches presented in each channel, it can be operated bi-directionally, which enables BFIC to be operated in the 8Tx8Rx TDD mode, as shown in Figure 2c. The BFIC is also able to operate in the four-channel mode. When the SPDT switches are on, the right side, the four-channel can be made to work in Tx mode and the left side four-channel can be made to work in Rx mode, as shown in Figure 2d. Hence, the BFIC can operate in the 4Tx and 4Rx mode independently. The bias, phase, and amplitude controls for each channel are digitally controlled by the SPI. Furthermore, the bandgap voltage reference (BGR), low drop output (LDO) regulator, and electrostatic discharge (ESD) protection circuits are integrated into the eight-channel BFIC to provide a stable DC bias.
The differential amplifier is designed with a transformer-coupled structure, which has the advantage of not requiring a DC-blocking capacitor and RF choke and also improves the bandwidth [[
The equivalent circuit diagram of the Tx mode of the bi-directional amplifier is shown in Figure 4a. The Tx mode output stage is designed with common-source topology for high linearity. Figure 4b shows the Rx mode of the bi-directional amplifier. The Rx mode input stage is designed with cascode amplifier topology for high isolation between the input and the output ports. The proposed circuit configuration does not need additional SPDT switches for bi-directional operation, which reduces the chip area as well as insertion loss in the Tx and Rx modes. Furthermore, the inductors can be shared for both modes, resulting in the reduction of inductors.
Figure 5a shows the simulated s-parameter results, and Figure 5b shows the power characteristics measurement of a differential two-stage bi-directional amplifier in the transmit mode. The transmitter-mode reference gain is 6.6 dB and output P1dB, and saturation power PSAT are −2.2 dBm and 5.6 dBm at 28 GHz. Figure 6a shows the simulated s-parameter results, and Figure 6b shows the power characteristics measurement of a differential two-stage bi-directional amplifier in the receive mode. The receiver-mode reference gain is 8.1 dB, and output P1dB and saturation power PSAT are −5.9 dBm and 2.8 dBm, respectively, at 28 GHz.
The schematics of the proposed six-bit differential phase shifter and three-bit digital step attenuator, including the tuning bit, are shown in Figure 7. The phase shifter and attenuator are designed with a differential structure since it has advantages, such as improved linearity and reduced coupling between the signals at different ports. The phase shifter and attenuator circuits are distributed in a single block to make the compact chip size. The phase shifter and attenuator bits are cascaded in such an order to obtain better input and output matching and lower insertion loss.
The switched filter phase shifters are attractive for mm-wave design due to their high linearity and lack of DC power consumption. In addition, it can be implemented with a compact size and low insertion loss because it consists of lumped components, including NMOS transistor switches [[
The attenuator is used in calibrating amplitude error as well as sidelobe level reduction in the radiation pattern of an antenna. For zero DC power consumption, the attenuator is designed in a passive type, which is beneficial to be used in a large-scale phased array antenna system. Various topologies are available for the design of attenuators, including the switched path type, the distributed type, and the switched Pi/T-type attenuator [[
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The differential 8 dB and 16 dB attenuators are designed using a switched T-type structure. The differential 4 dB attenuator and 1 dB attenuator are implemented with the shunt resistors, R
A power divider is implemented in the BFIC to split or combine the multiple channels transmit/receive signals. The two-way power divider is designed with differential structures, which is robust to parasitic inductances to the ground paths. The chip size is reduced using an artificial transmission line instead of the quarter-wavelength transmission line used in a conventional two-way power divider [[
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The inductance and capacitance in a differential two-way power divider are determined by Equation (
The Marchand balun is implemented in transforming single-ended and differential signals. The Marchand balun is attractive due to its wideband performance, employing quarter wavelength coupled line sections. Figure 11 shows the schematic of the Marchand balun. The quarter-wavelength transmission lines are implemented as a vertically coupled structure, and the shunt capacitor helps compensate for impedance matching. Figure 12 shows the simulated insertion loss, return losses, and phase differences between differential output paths. The insertion losses of P1 to P2 and P1 to P3 are −6.3 dB and −6.7 dB at 27–29.5 GHz, respectively. The simulated return losses at each port are under 10 dB at 26–32 GHz, and the simulated phase difference is 176° at 26–32 GHz.
A fully differential SPDT switch is designed to have high-power-handling capabilities for both the Tx and Rx paths and to have parasitic inductance robust performance as the CMOS switch structure has high insertion loss and low-power characteristics in high frequency. The body-floating technology is widely used in the CMOS switch to reduce insertion loss and improve power characteristics [[
The gain and phase control for each channel is digitally controlled by the SPI. The timing diagram of the 16-bit SPI is shown in Figure 15. The SPI configuration utilized SPI mode 0 with a CPOL (clock polarity) of 0 and a CPHA (clock phase) of 0 where the data is sampled on the clock's rising edge and shifted on the falling edge. The SPI protocol for the BFIC involves a 16-bit register where the first bit represents the read/write mode, seven bits represent the address, and the subsequent eight bits represent the data. When executing a write operation, the first bit of the address byte is set as '0'. The desired seven-bit address is assigned to the address field, and the eight-bit data field is filled with the required control information for the phase shifter, attenuator, and bias operation. To perform the read operation, the first bit of the address byte is set as '0'. The SPI interface supports a maximum operating speed of 20 MHz. The SPI design has been synthesized using Verilog code. The layout of the synthesized SPI block is shown in Figure 16. The size of the synthesized SPI block is 0.30 × 0.44 mm
The microphotograph of the fabricated 28 GHz eight-channel multimode BFIC fabricated in a commercial 65 nm CMOS technology is shown in Figure 17. The total area of the BFIC is 3.0 × 3.5 mm
Figure 18 shows the on-wafer S-parameter measurement of the 28 GHz CMOS BFIC using a network analyzer. The short, open, load, and thru (SOLT) calibration was performed with the on-wafer probe station. The power characteristics are measured with the signal source and the spectrum analyzer. Figure 19 shows the on-wafer power characteristic measurement setup using the spectrum analyzer. This measurement method requires calibration from the measurement equipment port to the RF probe tip, including RF cables.
Figure 20 shows the microphotograph of the fabricated 28 GHz differential two-stage bi-directional amplifier. The use of the transformer-coupled structure makes the compact chip size. The chip size of the differential two-stage bi-directional amplifier is 0.44 × 0.28 mm
Figure 24a shows the measured S-parameter results in the Tx mode of the eight-channel BFIC. The measured Tx mode gain is around 11 dB, and return losses are under 10 dB at 27.0–29.5 GHz. Figure 24b shows the measured power characteristics in the Tx mode. The measured Tx mode outputs, P
Table 1 summarizes the performance of this work and compares it with previously published 28 GHz beamforming ICs. The 28 GHz eight-channel multimode BFIC is designed with a differential structure to reduce interference from adjacent channels. The differential structure also allows common-mode rejection and less coupled signal at each port for multi-channel. The proposed BFIC has comparable RMS phase and amplitude error than the same RF phase-shifting architecture. The proposed BFIC allows for multimode operation based on the number of antenna requirements. The single BFIC is capable of operating in 8Tx and 8Rx modes separately as well as in a combined 8Tx8Rx TDD mode. Furthermore, it is capable of operating in four-channel mode, allowing the independent operation of 4Tx and 4Rx within a single BFIC.
This paper presents a multimode 28 GHz fully differential eight-channel BFIC in 65 nm CMOS technology for phased array transceivers. The bi-directional amplifier is implemented with a transformer coupled structure for compactness and low insertion loss. The cross connected quad switch type 180° phase bit and a differential two-way power divider using artificial transmission lines make the design compact and lower power consumption. The chip size is 3.0 × 3.5 mm
DIAGRAM: Figure 1 Block diagram of 28 GHz eight-channel multimode beamforming IC.
DIAGRAM: Figure 2 Simplified block diagram of multimode operation of 28 GHz eight-channel CMOS beamforming IC: (a) 8Tx mode, (b) 8Rx mode, (c) 8Tx8Rx TDD mode, and (d) 4Tx and 4Rx independent mode.
Graph: Figure 3 Schematic of the transformer coupled differential two-stage bi-directional amplifier.
DIAGRAM: Figure 4 Equivalent circuit diagram of the differential two-stage bi-directional amplifier: (a) Tx mode and (b) Rx mode.
Graph: Figure 5 Simulated results of differential two−stage bi−directional amplifier in Tx−mode: (a) s−parameter (b) power characteristics.
Graph: Figure 6 Simulated results of differential two−stage bi−directional amplifier in Rx−mode: (a) s−parameter and (b) power characteristics.
Graph: Figure 7 Schematic of the six-bit phase shifter and the three-bit digital step attenuator with tuning bit.
Graph: Figure 8 Simulated results: (a) phase difference of six-bit phase shifter and (b) amplitude difference of three-bit attenuator.
Graph: Figure 9 Schematic of the differential two-way power divider.
Graph: Figure 10 Simulation results of the differential two−way power divider.
Graph: Figure 11 Schematic of the Marchand balun.
Graph: Figure 12 Simulation results of the Marchand balun.
Graph: Figure 13 Schematic of the differential SPDT switch.
Graph: Figure 14 Simulation results of the differential SPDT switch.
DIAGRAM: Figure 15 Timing diagram of the 16-bit SPI.
Graph: Figure 16 Layout of the synthesized SPI block.
Graph: Figure 17 Microphotograph of the proposed 28 GHz CMOS eight-channel multimode beamforming IC.
Graph: Figure 18 Measurement setup of on-wafer S-parameter of 28 GHz CMOS beamforming IC.
Graph: Figure 19 Measurement setup of on-wafer power characteristics of 28 GHz CMOS beamforming IC.
Graph: Figure 20 Microphotograph of the proposed differential two-stage bi-directional amplifier.
Graph: Figure 21 Measured Tx mode differential bi−directional amplifier: (a) S−parameters and (b) power characteristics.
Graph: Figure 22 Measured Rx mode differential bi−directional amplifier: (a) S−parameters and (b) power characteristics.
Graph: Figure 23 Measured RMS errors of the differential bi−directional amplifier with (a) Tx mode attenuation control and (b) Rx mode attenuation control.
Graph: Figure 24 Measured Tx mode: (a) S−parameters and (b) power characteristics.
Graph: Figure 25 Measured Rx mode S−parameters.
Graph: Figure 26 Measured (a) phase characteristics and (b) attenuation characteristics.
Graph: Figure 27 Measured RMS errors with (a) phase control and (b) attenuation control.
Table 1 Summary of 28 GHz multimode beamforming IC for phased array transceiver.
Ref. This Work [ [ [ Tech (CMOS) 65 nm 65 nm 65 nm 28 nm Freq. (GHz) 27.0–29.5 26.5–30 26.5–29.5 25.8–28 Number of channels 8 TRx 4TRx 4 TRx 8 TRx Single-ended/Differential Differential Differential Differential Single-ended Tx/Rx Gain (dB) 11/9 18.6/14.8 9/11 N/A P1dB/PSAT (dBm) −2.5/1.3 13.3/- 15.7/18 9.5/10.5 Phase shift step (o) 6 bit/5.6 6 bit/5.6 2 + 3 + 10 bit/0.3 ** 3 bit/45 RMS amplitude error (dB) 0.6 0.21 0.04 1 RMS phase error (o) 3.2 1.4 0.3 7 Tx/Rx PDC of 1channel (mW) 181/181 73/- 299/148 85/50 * Mode 8Tx only 4Tx only 4Tx only 8Tx only Chip Size (mm2) 10.5 0.92 *** 12 7.3
Conceptualization, A.B., J.P. and J.-G.K.; methodology, A.B., J.P. and J.-G.K.; investigation, A.B., J.P. and J.-G.K.; writing—original draft preparation, A.B., J.P. and J.-G.K.; writing—review and editing, A.B. and J.-G.K.; supervision, D.B. and J.-G.K.; project administration, D.B. and J.-G.K.; funding acquisition, J.-G.K. All authors have read and agreed to the published version of the manuscript.
Not applicable.
Not applicable.
The data can be obtained from the authors on request.
The authors declare no conflict of interest.
By Ayush Bhatta; Jeongsoo Park; Donghyun Baek and Jeong-Geun Kim
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