Performance analysis of CMOS mode locked class E power amplifier
In: 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010),Seattle, WA,AUG 01-04, 2010
Online
report
Zugriff:
The design of Class E Amplifiers is more difficult than other type of amplifiers as it is imposed by time domain constraints. This paper presents the performance analysis of Mode Locked class E Power Amplifiers using State Space Analysis Algorithm. A technique is introduced which is used to curb the negative effect of parasitic resistance of DC Feed Choke and the Power Amplifier operates at 2.4GHz and simulated with a 0.18 mu m CMOS process at a supply voltage of 2V.
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Performance analysis of CMOS mode locked class E power amplifier
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Autor/in / Beteiligte Person: | ARORA, P ; MUKHERJEE, J ; AGARWAL, V |
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Zeitschrift: | 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010),Seattle, WA,AUG 01-04, 2010 |
Veröffentlichung: | IEEE, 2010 |
Medientyp: | report |
ISBN: | 978-1-4244-7773-9 (print) ; 1-4244-7773-5 (print) |
ISSN: | 1548-3746 (print) |
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