13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization
In: 2024 IEEE International Solid-State Circuits Conference (ISSCC, 2024
Online
Konferenz
Zugriff:
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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization
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Autor/in / Beteiligte Person: | Lee, Jinhyung ; Cho, Kyungjun ; Lee, Chang Kwon ; Lee, Yeonho ; Park, Jae-Hyung ; Oh, Su-Hyun ; Ju, Yucheon ; Jeong, Chunseok ; Cho, Ho Sung ; Lee, Jaeseung ; Yun, Tae-Sik ; Cho, Jin Hee ; Oh, Sangmuk ; Moon, Junil ; Park, Young-Jun ; Choi, Hong-Seok ; Kim, In-Keun ; Yang, Seung Min ; Kim, Sun-Yeol ; Jang, Jaemin ; Kim, Jinwook ; Lee, Seong-Hee ; Jeon, Younghyun ; Park, Juhyung ; Kim, Tae-Kyun ; Ka, Dongyoon ; Oh, Sanghoon ; Kim, Jinse ; Jeon, Junyeol ; Kim, Seonhong ; Kim, Kyeong Tae ; Kim, Taeho ; Yang, Hyeonjin ; Yang, Dongju ; Lee, Minseop ; Song, Heewoong ; Jang, Dongwook ; Shin, Junghyun ; Kim, Hyunsik ; Baek, Changki ; Jeong, Hajun ; Yoon, Jongchan ; Lim, Seung-Kyun ; Lee, Kyo Yun ; Koo, Young Jun ; Park, Myeong-Jae ; Cho, Joohwan ; Kim, Jonghwan |
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Zeitschrift: | 2024 IEEE International Solid-State Circuits Conference (ISSCC, 2024 |
Veröffentlichung: | IEEE, 2024 |
Medientyp: | Konferenz |
DOI: | 10.1109/isscc49657.2024.10454440 |
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