First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm
In: 2014 VLSI-Technology Technical Digest ; 2014 IEEE Symposium on VLSI Technology ; https://hal.science/hal-02003853 ; 2014 IEEE Symposium on VLSI Technology, Jun 2014, Honolulu, United States. pp.66-67, ⟨10.1109/VLSIT.2014.6894369⟩, 2014
Konferenz
Zugriff:
session 8: Beyond CMOS ; International audience ; We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x Ge x (x=0, 0.2, 0.25) nanowires, Si 0.7 Ge 0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W -3 dependence of ON current (I ON ) per wire. The fabricated devices exhibit higher I ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.
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First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm
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| Autor/in / Beteiligte Person: | Villalon, A. ; Le Royer, C. ; Nguyen, P. ; Barraud, S. ; Glowacki, F. ; Revelant, A. ; Selmi, L. ; Cristoloveanu, S. ; Tosti, L. ; Vizioz, C. ; Hartmann, J. M. ; Bernier, N. ; Previtali, B. ; Tabone, C. ; Allain, F. ; Martinie, S. ; Rozeau, O. ; Vinet, M. ; Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI) ; Direction de Recherche Technologique (CEA) (DRT (CEA)) ; Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA) ; Centre Hospitalier Régional Universitaire CHU Lille (CHRU Lille) ; Università degli Studi di Udine - University of Udine Italie ; Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB Université de Savoie Université de Chambéry )-Centre National de la Recherche Scientifique (CNRS) ; ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010) ; European Project: 257267,ICT,FP7-ICT-2009-5,STEEPER(2010) |
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| Zeitschrift: | 2014 VLSI-Technology Technical Digest ; 2014 IEEE Symposium on VLSI Technology ; https://hal.science/hal-02003853 ; 2014 IEEE Symposium on VLSI Technology, Jun 2014, Honolulu, United States. pp.66-67, ⟨10.1109/VLSIT.2014.6894369⟩, 2014 |
| Veröffentlichung: | HAL CCSD ; IEEE, 2014 |
| Medientyp: | Konferenz |
| DOI: | 10.1109/VLSIT.2014.6894369 |
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