A Novel Full Automatic Layout Generation Strategy For Static CMOS Circuits : Very large scale integration of system on chip; VLSI-SOC, IFIP TC 10/WG 10.5
In: INTERNATIONAL FEDERATION FOR INFORMATION PROCESSING -PUBLICATIONS- IFIP (NO 200):197-212; (2006) NO 200, S. 197-212
Konferenz
Zugriff:
Titel: |
A Novel Full Automatic Layout Generation Strategy For Static CMOS Circuits : Very large scale integration of system on chip; VLSI-SOC, IFIP TC 10/WG 10.5
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Autor/in / Beteiligte Person: | Lazzari, C. ; Domingues, C. ; Guntzel, J. ; Reis, R. |
Link: | |
Quelle: | INTERNATIONAL FEDERATION FOR INFORMATION PROCESSING -PUBLICATIONS- IFIP (NO 200):197-212; (2006) NO 200, S. 197-212 |
Veröffentlichung: | 2006 |
Medientyp: | Konferenz |
ISBN: | 978-0-387-33402-8 (print) ; 0-387-33402-5 (print) |
ISSN: | 1571-5736 (print) |
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