A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
In: IEEE journal of solid-state circuits, Jg. 57 (2022), Heft 12, S. 3527-3537
Online
serialPeriodical
Zugriff:
Titel: |
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
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Autor/in / Beteiligte Person: | Park, Hangi ; Hwang, Chanwoong ; Seong, Taeho ; Choi, Jaehyouk |
Link: | |
Zeitschrift: | IEEE journal of solid-state circuits, Jg. 57 (2022), Heft 12, S. 3527-3537 |
Veröffentlichung: | 2022 |
Medientyp: | serialPeriodical |
ISSN: | 0018-9200 (print) |
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