Zastosowanie pakietów Alliance i Magic w projektowaniu topografii cyfrowych układów scalonych CMOSUse of Alliance and Magic systems in layout design process of digital CMOS integrated circuits
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Zugriff:
The main subject of this paper are issues of layout design of digital Integrated Circuits using VHDL language and the Alliance tool. We present how a designer may automatically generate a layout of his circuits starting with a file containing a VHDL-code. The 16-bit sumator is shown as an example of students project exercise. Moreover, we discuss differences between the Standard Cell structure and manually designed layouts.
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Zastosowanie pakietów Alliance i Magic w projektowaniu topografii cyfrowych układów scalonych CMOSUse of Alliance and Magic systems in layout design process of digital CMOS integrated circuits
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Autor/in / Beteiligte Person: | Solecki, M. ; Pankiewicz, B. ; Felendzer, Z. |
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Medientyp: | serialPeriodical |
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