Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance
In: 10th SASIMI workshop, Nara, Japan, 2001Microelectronics journal 33(11):1027-1031; Jg. 33 (2002) 11, S. 1027-1031
Konferenz
- print, 14 ref
Zugriff:
The intrinsic channel resistance, which is caused by the finite charging time of the carriers in the inversion layer, has remarkable impact on RF CMOS circuits, especially low noise amplifier (LNA), the first block of receiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed in this paper, and then new formulae are proposed systematically. Moreover, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.
Titel: |
Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance
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Autor/in / Beteiligte Person: | JIWEI, CHEN ; BINGXUE, SHI |
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Quelle: | 10th SASIMI workshop, Nara, Japan, 2001Microelectronics journal 33(11):1027-1031; Jg. 33 (2002) 11, S. 1027-1031 |
Veröffentlichung: | Oxford: Elsevier Science, 2002 |
Medientyp: | Konferenz |
Umfang: | print, 14 ref |
ISSN: | 0959-8324 (print) |
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