Structure independent representation of output transition time for CMOS library
In: Integrated circuit design (Seville, 11-13 September 2002)Lecture notes in computer science :247-257
Konferenz
- print, 16 ref
Zugriff:
Non zero signal rise and fall times significantly contribute to the gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macro-model of the timing performance of CMOS structures, we present in this paper a general representation of transition times allowing fast and accurate cell performance evaluation. This general representation is then exploited to define a robust characterization protocol of the output transition time of standard cells. Both the representation and the protocol are finally validated comparing calculated gate input-output transition time values with standard look-up representation obtained from Hspice simulations (Bsim3v.3, level 69, 0.25μm process).
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Structure independent representation of output transition time for CMOS library
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Autor/in / Beteiligte Person: | MAURINE, P ; AZEMARD, N ; AUVERGNE, D |
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Quelle: | Integrated circuit design (Seville, 11-13 September 2002)Lecture notes in computer science :247-257 |
Veröffentlichung: | Berlin: Springer, 2002 |
Medientyp: | Konferenz |
Umfang: | print, 16 ref |
ISSN: | 0302-9743 (print) |
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