Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits
In: IEEE 2004 Custom Integrated Circuits Conference (CICC 2004)IEEE journal of solid-state circuits 40(9):1787-1796; Jg. 40 (2005) 9, S. 1787-1796
Online
Konferenz
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Zugriff:
In nanoscale CMOS circuits the random dopant fluctuations (RDF) cause significant threshold voltage (Vt) variations in transistors. In this paper, we propose a semi-analytical estimation methodology to predict the delay distribution [Mean and Standard Deviation (STD)] of logic circuits considering Vt variation in transistors. The proposed method is fast and can be used to predict delay distribution in nanoscale CMOS technologies both at the circuit and the device design phase. The method is applied to predict the delay distributions in different logic gates and flip-flops and is verified with detail Monte Carlo simulations. It is observed that a 30% spread (STD/Mean) in Vt variation results in 5% spread in the delay of logic gates (inverter, NAND, etc.). The effect of Vt variation due to RDF is more significant in the setup time (STD/Mean = 11%) and clock-to-output delay (STD/Mean = 5% to 25%) of flip-flops.
Titel: |
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits
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Autor/in / Beteiligte Person: | MAHMOODI, Hamid ; MUKHOPADHYAY, Saibal ; ROY, Kaushik |
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Quelle: | IEEE 2004 Custom Integrated Circuits Conference (CICC 2004)IEEE journal of solid-state circuits 40(9):1787-1796; Jg. 40 (2005) 9, S. 1787-1796 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2005 |
Medientyp: | Konferenz |
Umfang: | print, 15 ref |
ISSN: | 0018-9200 (print) |
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