A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS
In: IEEE 2004 Custom Integrated Circuits Conference (CICC 2004)IEEE journal of solid-state circuits 40(9):1932-1939; Jg. 40 (2005) 9, S. 1932-1939
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Zugriff:
This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54°/1.1° for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5 dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.
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A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS
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Autor/in / Beteiligte Person: | PENGFEI, ZHANG ; DER, Lawrence ; GOWDER, Sujatha ; HART, Siegfried ; HUYNH, Lam ; NGUYEN, Thai ; RAZAVI, Behzad ; DAWEI, GUO ; SEVER, Isaac ; BOURDI, Taoufik ; LAM, Christopher ; ZOLFAGHARI, Alireza ; CHEN, Jess ; GAMBETTA, Douglas ; BAOHONG, CHENG |
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Quelle: | IEEE 2004 Custom Integrated Circuits Conference (CICC 2004)IEEE journal of solid-state circuits 40(9):1932-1939; Jg. 40 (2005) 9, S. 1932-1939 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2005 |
Medientyp: | Konferenz |
Umfang: | print, 20 ref |
ISSN: | 0018-9200 (print) |
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