Power-clock gating in adiabatic logic circuits
In: Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 638-646
Konferenz
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Zugriff:
For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption caused by leakage currents, Power-Gating has been introduced. This paper presents for the first time Clock-Gating and Power-Gating in Adiabatic Logic. As the oscillator signal is both the power and the clock in Adiabatic Logic, a Power-Clock Gating is implemented using a switch to detach the adiabatic logic block from the oscillator. Depending on the technology the optimum switch topology and dimension is discussed. This paper shows that a boosted n-channel MOSFET as well as a transmission gate are good choices as a switch. Adiabatic losses are reduced greatly by shutting down idle adiabatic circuit blocks with Power-Clock Gating.
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Power-clock gating in adiabatic logic circuits
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Autor/in / Beteiligte Person: | TEICHMANN, Philip ; FISCHER, Jurgen ; HENZLER, Stephan ; AMIRANTE, Ettore ; SCHMITT-LANDSIEDEL, Doris |
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Quelle: | Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 638-646 |
Veröffentlichung: | Berlin: Springer, 2005 |
Medientyp: | Konferenz |
Umfang: | print, 8 ref |
ISSN: | 0302-9743 (print) |
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